Title :
Active circuit to through silicon via (TSV) noise coupling
Author :
Cho, Jonghyun ; Shim, Jongjoo ; Song, Eakhwan ; Pak, Jun So ; Lee, Junho ; Lee, Hyungdong ; Park, Kunwoo ; Kim, Joungho
Author_Institution :
Div. of Electr. Eng., KAIST, Daejeon, South Korea
Abstract :
In this paper, we propose a coupling model between through silicon via (TSV) and substrate based on a 3-Dimensional transmission line matrix (3D-TLM), which utilizes equivalent lumped circuit model of silicon substrate and TSV. The proposed model is verified by S-parameter simulations using a 3D field solver and analyzed with various structural parameters: TSV diameter, distance between TSV and noise source, and silicon substrate height. Based on the model, timing jitter degradation on phase locked loop (PLL) caused by substrate noise coupling is investigated. A shielding technique using a guard ring structure is applied to suppress the coupling noise.
Keywords :
S-parameters; active networks; circuit noise; elemental semiconductors; equivalent circuits; phase locked loops; silicon; substrates; timing jitter; transmission line matrix methods; 3D field solver; S-parameter simulations; Si; TSV; active circuit; coupling model; equivalent lumped circuit model; guard ring structure; phase locked loop; shielding technique; structural parameters; substrate noise coupling; three-dimensional transmission line matrix; through silicon via; timing jitter degradation; Active circuits; Active noise reduction; Circuit noise; Coupling circuits; Distributed parameter circuits; Phase locked loops; Scattering parameters; Silicon; Through-silicon vias; Transmission line matrix methods;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems, 2009. EPEPS '09. IEEE 18th Conference on
Conference_Location :
Portland, OR
Print_ISBN :
978-1-4244-4447-2
Electronic_ISBN :
978-1-4244-5646-8
DOI :
10.1109/EPEPS.2009.5338469
