Clamped inductive turn-off failure in high-voltage NPT-IGBTs under overloading conditions

Author

Perpiñà, X. ; Cortés, I. ; Urresti-Ibañez, J. ; Jordà, X. ; Rebollo, J. ; Millán, J.

Author_Institution

Inst. de Microelectron. de Barcelona IMB-CNM, Barcelona, Spain

fYear

2012

fDate

3-7 June 2012

Firstpage

361

Lastpage

364

Abstract

The clamped inductive turn-off failure of NPT-IGBTs is investigated under overloading events. First, their signatures are determined. Second, physical TCAD simulations are carried out considering, for the first time, the current mismatch among the cells from the chip core, gate runner and edge termination areas. As a result, a secondary breakdown at the IGBT peripheral cells at the edge of the gate runner has been indentified to be responsible of the failure. Besides, a strategy to enhance the device robustness is proposed.

Keywords

insulated gate bipolar transistors; semiconductor device breakdown; technology CAD (electronics); IGBT peripheral cell; chip core; clamped inductive turn-off failure; current mismatch; edge termination area; gate runner; high-voltage NPT-IGBT; overloading condition; physical TCAD simulation; secondary breakdown; Buffer layers; Computational modeling; Current density; Insulated gate bipolar transistors; Integrated circuit modeling; Logic gates;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs (ISPSD), 2012 24th International Symposium on

Conference_Location

Bruges

ISSN

1943-653X

Print_ISBN

978-1-4577-1594-5

Electronic_ISBN

1943-653X

Type

conf

DOI

10.1109/ISPSD.2012.6229096

Filename

6229096