High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

Author

Bolchini, C. ; Miele, A. ; Sandionigi, C. ; Ottavi, M. ; Pontarelli, S. ; Salsano, A. ; Metra, C. ; Omaña, M. ; Rossi, D. ; Reorda, M. Sonza ; Sterpone, L. ; Violante, M. ; Gerardin, S. ; Bagatin, M. ; Paccagnella, A.

Author_Institution

Dip. Elettron. e Inf., Politec. di Milano, Milan, Italy

fYear

2012

fDate

3-5 Oct. 2012

Firstpage

121

Lastpage

125

Abstract

This paper reports the main contribution of a project devoted to the definition of techniques to design and evaluate fault tolerant systems implemented using the SoPC paradigm, suitable for missionand safety-critical application environments. In particular, the effort of the five involved research units has been devoted to address some of the main issues related to the specific technological aspects introduced by these flexible platforms. The overall target of the research is the development of a design methodology for highly reliable systems realized on reconfigurable platforms based on a System-on-Programmable Chip (SoPC), as discussed in the next section.

Keywords

fault tolerance; integrated circuit design; integrated circuit reliability; system-on-chip; SoPC paradigm; design methodologies; high-reliability fault tolerant digital systems; mission-critical application environments; nanometric technologies; reconfigurable platforms; safety-critical application environments; system-on-programmable chip; Circuit faults; Computer aided manufacturing; Fault tolerance; Fault tolerant systems; Program processors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2012 IEEE International Symposium on

Conference_Location

Austin, TX

Print_ISBN

978-1-4673-3043-5

Type

conf

DOI

10.1109/DFT.2012.6378211

Filename

6378211