Scan testing of asynchronous sequential circuits

Author

Petlin, O.A. ; Furber, S.B.

Author_Institution

Dept. of Comput. Sci., Oxford Univ., UK

fYear

1995

fDate

16-18 Mar 1995

Firstpage

224

Lastpage

229

Abstract

A method to design and test asynchronous sequential circuits (ASCs) based on the micropipeline design style is presented in this paper. According to the proposed scan test approach the combinational block is tested separately by scanning the test vectors in and shifting the responses out of the state registers. This provides for the detection of all single stuck-at and delay faults in the ASC under test. The complexity of the test procedure of such a testable ASC is reduced to that of the combinational circuit. Tests for the combinational circuit and state holding elements can be derived using standard test generation techniques

Keywords

VLSI; asynchronous circuits; asynchronous sequential logic; boundary scan testing; delays; integrated circuit testing; integrated logic circuits; logic design; logic testing; sequential circuits; asynchronous sequential circuits; combinational block; delay faults; micropipeline design style; scan testing; single stuck-at faults; standard test generation techniques; state holding elements; Circuit faults; Circuit testing; Combinational circuits; Delay; Design methodology; Electrical fault detection; Fault detection; Registers; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on

Conference_Location

Buffalo, NY

ISSN

1066-1395

Print_ISBN

0-8186-7035-5

Type

conf

DOI

10.1109/GLSV.1995.516057

Filename

516057