A low overhead built-in delay testing with voltage and frequency adaptation for variation resilience

Process variations and circuit aging continue to be a main challenge to the power-efficiency of VLSI circuits, as considerable power budget must be allocated at design time to mitigate timing variations. Modern designs incorporate adaptive techniques for variation compensation to reduce the extra power consumption. Composing an efficient adaptation system requires low cost techniques for delay variation detection as well as handling the variations. This work presents an area-efficient built-in delay testing scheme which exploits BIST SCAN architecture and dynamic clock skew control to minimize overheads induced by detection circuitry. Using this built-in delay testing scheme, we propose a fine-grained adaptation system utilizing boostable repeater design in conjunction with adaptive clock skew control to compensate variations detected. The proposed adaptive system is compared against conventional approaches through SPICE simulations with 45nm technology from PTM. The results demonstrate that the proposed system efficiently mitigates process variation and aging induced timing degradations with 26% less power consumption, while occupying 7.2% of extra die area overhead.