Title :
Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test
Author :
Pottinger, Hardy J. ; Lin, Chien-Yuh
Author_Institution :
Dept. of Electr. Eng., Missouri Univ., Rolla, MO, USA
Abstract :
The XC4000 Logic Cell Array Family of field programmable gate arrays developed by Xilinx includes support for the IEEE Standard 1149.1 Test Access Port and Boundary Scan Architecture. Boundary-scan with built-in self-test is known to provide tests of high quality. The design and implementation of boundary-scan with built-in self-test that conforms fully to the IEEE Standard 1149.1 for the XC4000 device is presented. Fault simulation was performed to evaluate the effectiveness of the built-in self-test. Hardware was realized with the XC4003PC84-6 used on the Xilinx demo board. The boundary scan and self test logic was controlled via the widely available parallel printer port of an IBM compatible PC. This results in an ideal hardware/software combination for use in teaching and demonstrating boundary scan and self-test principles
Keywords :
boundary scan testing; built-in self test; computer science education; design for testability; educational aids; electronic engineering education; field programmable gate arrays; integrated circuit design; integrated circuit testing; logic design; logic testing; student experiments; BIST; IEEE Standard 1149.1; XC4000 Logic Cell Array Family; XC4003PC84-6; Xilinx; boundary scan; built-in self-test; demonstration; fault simulation; field programmable gate array; reconfigurable FPGA; teaching; Automatic testing; Built-in self-test; Field programmable gate arrays; Hardware; Logic testing; Performance evaluation; Programmable logic arrays; Reconfigurable logic; Software testing; Standards development;
Conference_Titel :
VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on
Conference_Location :
Buffalo, NY
Print_ISBN :
0-8186-7035-5
DOI :
10.1109/GLSV.1995.516060
