On unified architectures for synthesizing and implementation of fast parametric transforms

In this paper a methodology to design VLSI architectures for parametric transform families is proposed. A parametric transform family consists of discrete orthogonal transforms such that they all may be computed with a fast algorithm of similar structure where parameters defining the transform within the family are used. In our previous work, an algorithm to synthesize transforms with predefined basis functions was introduced and efficiently applied to image compression. The methodology proposed in this paper allows of designing VLSI architectures that may not only switch from one transform of a family to another by setting parameters, but also to actually set these parameters so that the matrix of the resulting transform has predefined basis functions