1.7-W 50-Gbit/s InP HEMT 4:1 multiplexer IC with a multi-phase clock architecture

Author

Sano, K. ; Murata, K. ; Sugitani, S. ; Sugahara, H. ; Enoki, T.

Author_Institution

NTT Photonics Labs., NTT Corp., Kanagawa, Japan

fYear

2002

fDate

20-23 Oct. 2002

Firstpage

159

Lastpage

162

Abstract

Low-power and high-speed operation of a 4:1 multiplexer IC with a multi-phase clock architecture is reported. The architecture features a toggle-type flip-flop (TFF) that generates a four-phase clock, and a series-gated 4:1 selector (SEL). The fabricated IC using InP HEMTs operates at 50 Gbit/s error-free with 1.71-W power consumption and 1-Vpp output amplitude. The power consumption is less than 1/3 that of a conventional tree-type InP HEMT 4:1 multiplexer IC and is achieved without any reduction of operation speed and output amplitude.

Keywords

HEMT integrated circuits; III-V semiconductors; field effect digital integrated circuits; flip-flops; high-speed integrated circuits; indium compounds; low-power electronics; multiplexing equipment; optical communication equipment; time division multiplexing; timing; 1.7 W; 50 Gbit/s; InP; InP HEMT multiplexer IC; electrical TDM; four-phase clock; high-speed operation; low-power operation; multi-phase clock architecture; optical communication systems; series-gated selector; time-division-multiplexing; toggle-type flip-flop; Circuits; Clocks; Energy consumption; Flip-flops; Gallium arsenide; HEMTs; Indium phosphide; Master-slave; Multiplexing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 2002. 24th Annual Technical Digest

Conference_Location

Monterey, California, USA

ISSN

1064-7775

Print_ISBN

0-7803-7447-9

Type

conf

DOI

10.1109/GAAS.2002.1049051

Filename

1049051