50-Gbit/s 4-bit multiplexer/demultiplexer chip-set using InP HEMTs

Author

Sano, K. ; Murata, K. ; Sugitani, S. ; Sugahara, H. ; Enoki, T.

Author_Institution

NTT Photonics Labs., NKK Corp., Kanagawa, Japan

fYear

2002

fDate

20-23 Oct. 2002

Firstpage

207

Lastpage

210

Abstract

This paper reports on the 50-Gbit/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DMUX) chip-set using InP HEMTs. In order to achieve high and wide-range bit-rate operation, timing design inside the ICs was precisely executed. The packaged MUX and DMUX achieved 50 Gbit/s back-to-back error-free operation for 2/sup 31/-1 pseudo-random bit streams (PRBS). Furthermore, the MUX operated from 4 to 50 Gbit/s with >1 V/sub pp/ output amplitude, and the DMUX exhibited >180-degrees phase margin from 4 to 50 Gbit/s for 2/sup 31/-1 PRBS.

Keywords

HEMT integrated circuits; III-V semiconductors; demultiplexing equipment; indium compounds; integrated circuit design; integrated circuit packaging; integrated circuit testing; multiplexing equipment; optical communication equipment; time division multiplexing; timing; 4 bit; 4 to 50 Gbit/s; DMUX phase margin; ETDM; IC timing design; InP; InP HEMT based multiplexer/demultiplexer chip-set; MUX output amplitude; PRBS; back-to-back error-free operation; electrical-time division multiplexing; fiber-optic system transmission capacity; packaged MUX/DMUX; pseudo-random bit streams; wide-range bit-rate operation; Circuits; Clocks; Flip-flops; HEMTs; Heterojunction bipolar transistors; Indium phosphide; MODFETs; Multiplexing; Packaging; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 2002. 24th Annual Technical Digest

Conference_Location

Monterey, California, USA

ISSN

1064-7775

Print_ISBN

0-7803-7447-9

Type

conf

DOI

10.1109/GAAS.2002.1049061

Filename

1049061