An FPGA based diagnostic tool for jitter optimization in serial high-speed transceivers

We present an embedded jitter measurement system for on-chip diagnostics of serial high-speed interfaces. A Virtex-5 FPGA uses a 3Gbit reference signal to retrieve timing jitter distributions from a system under test (SUT). Using a recently developed fitting method, the total jitter of the system is determined, which allows for judging the quality of transmission lines, PLLs or transceiver structures. The diagnostic tool is thus able to optimize and configure the SUT without the use of an additional instrumentation device.