Title :
Simulation-based hierarchical sizing and biasing of analog firm IPs
Author :
Javid, Farakh ; Iskander, Ramy ; Louërat, Marie-Minerve
Author_Institution :
LIP6-SoC Lab., Univ. of Paris VI, Paris, France
Abstract :
This paper presents a simulation-based hierarchical sizing and biasing tool for analog integrated circuits design. The tool allows the designer to express the sizing procedure in terms of sizing and biasing operators. These operators are technology independent, hence the documented procedure can be easily ran over different technologies. A procedure has been proposed for a single-ended two-stage operational amplifier and evaluated over 130 nm, 65 nm and 45 nm technologies. The results prove the efficiency of the proposed tool.
Keywords :
analogue integrated circuits; integrated circuit design; operational amplifiers; analog firm IP; analog integrated circuit design; biasing; simulation-based hierarchical sizing; single-ended two-stage operational amplifier; Circuit faults; Circuit testing; Electrodes; Microfluidics; Micromechanical devices; Optimization; Routing; System testing; Transportation; Voltage control;
Conference_Titel :
Behavioral Modeling and Simulation Workshop, 2009. BMAS 2009. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-5358-0
DOI :
10.1109/BMAS.2009.5338891
