Trace and debug port based watchdog processor

Novel architectures and processors are designed to satisfy the needs specified by functional safety standards, like IEC 61508 and ISO 26262. An example for this devices is the TMS570 from Texas Instruments, which is a SIL3 (Safety Integrity Level 3) capable microcontroller. The question is whether a specialized hardware alone, like the TMS570 is enough for reaching safety goals or additional efforts should be done. This paper presents our novel idea of trace and debug port based watchdog processor that increase the safety for systems designed with traditional microcontrollers or with modern dual core safe ones. The approach presented is using the debug and trace hardware blocks (present in nearly every 32-bit microcontrollers introduced into the market in the last 5 years) to see inside the guarded system and to make statements of its healthiness. The paper shows the benefits and capability of such debug and trace hardware based watchdog control. We also introduce the bottlenecks of this approach and make suggestions to eliminate these, by making minor modifications to the existing trace blocks of the ARM CoreSight architecture.