DocumentCode :
2479478
Title :
Synchronous DRAM products evolutionize memory system design
Author :
Cosoroaba, Adrian B.
Author_Institution :
Fujitsu Microelectronics Inc., San Jose, CA, USA
fYear :
1995
fDate :
7-9 Mar 1995
Firstpage :
70
Lastpage :
72
Abstract :
Main memory devices, DRAMs, have traditionally quadrupled in size from one generation to the next with limited speed improvements. High speed SRAM caches have usually filled the bandwidth gap between MPU and DRAMs. Designers have recently realized that with the increased software complexity and MPU speed requirements, SRAM caches alone might not be able to provide the ultimate Performance/Cost solution. A new synchronous I/O structure has recently been developed for DRAMs (under the auspices of the joint electronic device engineering council, JEDEC) and set as the new standard for high performance devices called synchronous DRAMs
Keywords :
DRAM chips; memory architecture; JEDEC; MPU speed requirements; high performance devices; memory system design; synchronous DRAM products; synchronous I/O structure; Bandwidth; Clocks; Content addressable storage; Costs; Delay; Microelectronics; Random access memory; SDRAM; Software performance; Synchronous generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Southcon/95. Conference Record
Conference_Location :
Fort Lauderdale, FL
Print_ISBN :
0-7803-2576-1
Type :
conf
DOI :
10.1109/SOUTHC.1995.516079
Filename :
516079
Link To Document :
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