Design and Implementation of Low Power Hardware Encryption for Low Cost Secure RFID Using TEA

Author

Israsena, P.

Author_Institution

Nat. Electron. & Comput. Technol. Center, Thailand IC Design Incubator, Pathumtani

fYear

0

fDate

0-0 0

Firstpage

1402

Lastpage

1406

Abstract

This paper discusses the design and implementation of a hardware encryption core for low cost RFID using TEA algorithm. Low cost RFIDs have stringent requirements in terms of cost related to area and power consumption, making conventional encryption unsuitable. This paper proposes the use of TEA algorithm for medium security systems. Three new implementations based on multiple, single, and digit-serial adders are designed and evaluated for their suitability. It is found that the multiple-adder design meets the requirements with the lowest power consumption. Based on 0.35 mum CMOS implementation, the TEA core has an area of 0.21 mm and is estimated to consume 7.37 muW of power

Keywords

CMOS integrated circuits; adders; cryptography; radiofrequency identification; telecommunication security; 0.21 mm; 0.35 micron; 7.37 muW; CMOS implementation; RFID security; TEA core; multiple-adder design; power consumption; radiofrequency identification; tiny encryption algorithm; Algorithm design and analysis; Authentication; Costs; Cryptography; Energy consumption; Hardware; ISO standards; Power system security; Privacy; Radiofrequency identification; RFID; TEA; encryption; low-power;

fLanguage

English

Publisher

ieee

Conference_Titel

Information, Communications and Signal Processing, 2005 Fifth International Conference on

Conference_Location

Bangkok

Print_ISBN

0-7803-9283-3

Type

conf

DOI

10.1109/ICICS.2005.1689288

Filename

1689288