DocumentCode
2479607
Title
Model Checking For Fault Explanation
Author
Jiang, Shengbing ; Fuhrman, Thomas E. ; Jha, Sumit K.
Author_Institution
GM R&D, Warren, MI
fYear
2006
fDate
13-15 Dec. 2006
Firstpage
404
Lastpage
409
Abstract
Model checking is very effective at finding out even subtle faults in system designs. A counterexample is usually generated by model checking algorithms when a system does not satisfy the given specification. However, a counterexample is not always helpful in explaining and isolating faults in a system when the counterexample is very long, which is usually the case for large scale systems. As such, there is a pressing need to develop fault explanation and isolation techniques. In this paper, we present a new approach for the fault explanation and isolation in discrete event systems with LTL (linear-time temporal logic) specifications. The notion of fault seed is introduced to characterize the cause of a fault. The identification of the fault seed is further reduced to a model checking problem. An algorithm is obtained for the fault seed identification. An example is provided to demonstrate the effectiveness of the approach developed
Keywords
discrete event systems; fault tolerant computing; formal specification; temporal logic; discrete event system; fault explanation technique; fault isolation technique; linear-time temporal logic; model checking; Computer science; Discrete event systems; Fault diagnosis; Large-scale systems; Logic; Pressing; Research and development; USA Councils;
fLanguage
English
Publisher
ieee
Conference_Titel
Decision and Control, 2006 45th IEEE Conference on
Conference_Location
San Diego, CA
Print_ISBN
1-4244-0171-2
Type
conf
DOI
10.1109/CDC.2006.377556
Filename
4177810
Link To Document