Title :
Specification and Verification of Digital Logic and PLCs using an Automaton Model with Delays
Author :
Izumi, Satoru ; Yamanaka, Kazuhiro ; Kato, Yasushi ; Takahashi, Kaoru
Author_Institution :
Sendai Nat. Coll. of Technol.
Abstract :
Some techniques and languages which support the design of digital logic have been traditionally presented. In this paper, we propose a new automaton model which enables to concisely specify digital logic and PLCs including delay and time-control by introducing two kinds of delays. Moreover, we develop a support tool which can intelligibly simulate the behavior of a system specified by this automaton model
Keywords :
delays; logic design; programmable controllers; PLC; automaton model; delay; digital logic design; time-control; Animation; Automata; Circuit simulation; Delay effects; Digital systems; Educational institutions; Electronic mail; Hardware design languages; Logic design; Programmable control; PLC; automata; digital logic; specification; verification;
Conference_Titel :
Information, Communications and Signal Processing, 2005 Fifth International Conference on
Conference_Location :
Bangkok
Print_ISBN :
0-7803-9283-3
DOI :
10.1109/ICICS.2005.1689292
