Title :
Digital fault simulation and test development using JESIM
Author_Institution :
Paging Products Group, Motorola Inc., Boynton Beach, FL, USA
Abstract :
Too often the efforts of digital IC design verification and test are left until after the design has been completed. Sometimes these efforts are not dedicated until after the silicon has been fabricated. The cost, performance, functionality, speed and reliability of the chip are greatly impacted by the lack of proper requirement and preparation for test. This paper discusses the usefulness of the Digital Event and Test simulator “JESIM” for design verification, fault simulation, test vector generation and design for testability
Keywords :
design for testability; digital simulation; fault diagnosis; integrated circuit design; integrated circuit reliability; logic testing; JESIM; design for testability; digital IC design verification; digital fault simulation; fault simulation; functionality; reliability; test development; test vector generation; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Fabrication; Integrated circuit testing; Logic design; Logic testing;
Conference_Titel :
Southcon/95. Conference Record
Conference_Location :
Fort Lauderdale, FL
Print_ISBN :
0-7803-2576-1
DOI :
10.1109/SOUTHC.1995.516085
