DocumentCode :
2479824
Title :
Retrospective on “Power-Sensitive Multithreaded Architecture”
Author :
Seng, John S. ; Tullsen, Dean M. ; Cai, George Z N
Author_Institution :
Comput. Sci. Dept., California Polytech. State Univ., San Luis Obispo, AZ, USA
fYear :
2012
fDate :
Sept. 30 2012-Oct. 3 2012
Firstpage :
15
Lastpage :
16
Abstract :
This article provides a retrospective look at the research that went into the 2000 ICCD paper “Power-Sensitive Multithreaded Architecture”. At the time, simultaneous multithreading processors were soon to be commercially available and power consumption was proving to be a challenging design constraint. That research introduced optimizations that increased power and energy efficiency through multithreading, while maintaining performance. This article discusses the optimizations in the paper and discusses how processor designs have changed since its publication.
Keywords :
multi-threading; parallel architectures; performance evaluation; power aware computing; energy efficiency; energy efficient processors; multithreading processor design constraint; optimizations; performance maintenance; power consumption; power efficiency; power-sensitive multithreaded architecture; Computer architecture; Energy efficiency; Instruction sets; Multithreading; Optimization; Power demand; energy efficient processors; hardware multithreading; power consumption; simultaneous multithreading;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design (ICCD), 2012 IEEE 30th International Conference on
Conference_Location :
Montreal, QC
ISSN :
1063-6404
Print_ISBN :
978-1-4673-3051-0
Type :
conf
DOI :
10.1109/ICCD.2012.6378609
Filename :
6378609
Link To Document :
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