A 6 bit 25 GS/s flash interpolating ADC in 90 nm CMOS technology

Author

Lang, Felix ; Alpert, Thomas ; Ferenci, Damir ; Grözing, Markus ; Berroth, Manfred

Author_Institution

Inst. of Electr. & Opt. Commun. Eng., Univ. of Stuttgart, Stuttgart, Germany

fYear

2011

fDate

3-7 July 2011

Firstpage

117

Lastpage

120

Abstract

A 25 GS/s 6 bit flash interpolating ADC in 90 nm CMOS technology with an analog input bandwidth of 14 GHz is presented. The ADC is realized in a fourfold parallelized structure to increase the sampling rate and to increase the available settling time in the single ADCs. To improve the linearity several calibration methods are implemented in the circuit. The power consumption of the whole ADC is 2.3 W, resulting in a FOM of 1.9 pJ/step. The converter core area is 0.75 mm².

Keywords

CMOS digital integrated circuits; analogue-digital conversion; CMOS technology; analog input bandwidth; converter core area; flash interpolating ADC; fourfold parallelized structure; frequency 14 GHz; power 2.3 W; settling time; size 90 nm; word length 6 bit; CMOS integrated circuits; CMOS technology; Calibration; Clocks; Interpolation; Layout; OFDM; Analog-to-digital converter (ADC); CMOS; flash ADC; interpolation; reference ladder calibration;

fLanguage

English

Publisher

ieee

Conference_Titel

Ph.D. Research in Microelectronics and Electronics (PRIME), 2011 7th Conference on

Conference_Location

Trento

Print_ISBN

978-1-4244-9138-4

Electronic_ISBN

978-1-4244-9136-0

Type

conf

DOI

10.1109/PRIME.2011.5966231

Filename

5966231