Title :
A PRET microarchitecture implementation with repeatable timing and competitive performance
Author :
Liu, Isaac ; Reineke, Jan ; Broman, David ; Zimmer, Michael ; Lee, Edward A.
Author_Institution :
Univ. of California, Berkeley, Berkeley, CA, USA
fDate :
Sept. 30 2012-Oct. 3 2012
Abstract :
We contend that repeatability of execution times is crucial to the validity of testing of real-time systems. However, computer architecture designs fail to deliver repeatable timing, a consequence of aggressive techniques that improve average-case performance. This paper introduces the Precision-Timed ARM (PTARM), a precision-timed (PRET) microarchitecture implementation that exhibits repeatable execution times without sacrificing performance. The PTARM employs a repeatable thread-interleaved pipeline with an exposed memory hierarchy, including a repeatable DRAM controller. Our benchmarks show an improved throughput compared to a single-threaded in-order five-stage pipeline, given sufficient parallelism in the software.
Keywords :
DRAM chips; memory architecture; microprocessor chips; performance evaluation; pipeline processing; real-time systems; timing; PRET microarchitecture implementation; PTARM; average-case performance improvement; competitive performance; computer architecture designs; execution time repeatability; memory hierarchy; precision-timed ARM; real-time system testing validity; repeatable DRAM controller; repeatable thread-interleaved pipeline; repeatable timing; throughput improvement; Computer architecture; Hardware; Instruction sets; Pipelines; Random access memory; Registers; Timing;
Conference_Titel :
Computer Design (ICCD), 2012 IEEE 30th International Conference on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-3051-0
DOI :
10.1109/ICCD.2012.6378622
