A low energy HEVC sub-pixel interpolation hardware

Author

Kalali, Ercan ; Hamzaoglu, Ilker

Author_Institution

Fac. of Eng. & Natural Sci., Sabanci Univ., Istanbul, Turkey

fYear

2014

fDate

27-30 Oct. 2014

Firstpage

1218

Lastpage

1222

Abstract

Sub-pixel interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC) video encoder and decoder. Therefore, in this paper, a low energy HEVC sub-pixel (half-pixel and quarter-pixel) interpolation hardware, which uses Hcub multiplierless constant multiplication algorithm, is proposed. The proposed HEVC sub-pixel interpolation hardware, in the worst case, can process 30 quad full HD (3840×2160) video frames per second. It has up to 48% less energy consumption than original HEVC sub-pixel interpolation hardware.

Keywords

field programmable gate arrays; interpolation; video coding; FPGA; energy consumption; half-pixel interpolation hardware; high efficiency video coding video decoder; high efficiency video coding video encoder; low energy HEVC subpixel interpolation hardware; quad full HD video frames; quarter-pixel interpolation hardware; Adders; Energy consumption; Field programmable gate arrays; Finite impulse response filters; Hardware; Hardware design languages; Interpolation; FPGA; HEVC; Hardware Implementation; Low Energy; Sub-Pixel Interpolation;

fLanguage

English

Publisher

ieee

Conference_Titel

Image Processing (ICIP), 2014 IEEE International Conference on

Conference_Location

Paris

Type

conf

DOI

10.1109/ICIP.2014.7025243

Filename

7025243