Reconfigurable data flow engine for HEVC motion estimation

High Efficiency Video Coding (HEVC) standard achieves enhanced compression efficiency in comparison to previous standards, at the cost of a dramatic increase of the computational load. In order to cope with such computational requirements, and to challenge the real-time encoding of High Definition (HD) video sequences with the HEVC standard, we propose herein a reconfigurable architecture design for the most computationally demanding motion estimation module, considering highly efficient Full-Search Block-Matching algorithm. The proposed architecture supports Prediction Blocks (PBs) sizes ranging from 8×8 to 64×64 pixels (also considering non-square shapes), and search areas as large as 256×256 pixels. Furthermore, this reconfigurable approach leverages the trade-off between maximum performance and minimum resource usage. Experimental results show that the proposed architecture is able of achieving real-time motion estimation with more than 26.9 fps, for 1080p video formats, a 64×64 pixels search area and 1 reference frame, by relying on a Xilinx Virtex 5 FPGA implementation. Moreover, a performance superior to the NVIDIA Fermi-based GPU implementation, for up to 25%, was achieved.