Hardware architecture of the fast mode decision algorithm for H.265/HEVC

In this paper, a course of low complexity Fast Mode Decision (FMD) algorithms as well as the corresponding hardware architecture is presented. Firstly, the depth information of co-located block from previous frame is used to predict the size of current block. Then, for a certain sized block, the inter prediction residual is analyzed to determine whether to terminate current check or to skip some unnecessary modes and split to smaller size. Finally, the corresponding hardware architecture is proposed based on state machine mechanism. Simulation results show that these proposed algorithms reduce the encoding time by 40.8~ 70.3%, without incurring any noticeable performance degradation. Hardware synthesis results demonstrate that the proposed architecture achieves a max frequency of about 193 MHz.