Automatic assertion extraction in gate-level simulation using GPGPUs

Author

Ono, Shohei ; Matsumoto, Takeshi ; Fujita, Masahiro

Author_Institution

Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan

fYear

2012

fDate

Sept. 30 2012-Oct. 3 2012

Firstpage

522

Lastpage

523

Abstract

In modern VLSI designs, assertions play an important role to understand design intention and ensure correctness of designs. In this paper, we consider to generate assertions from simulation results. This assertion extraction is performed by examining whether a logical relation is satisfied among a set of signals. We propose to accelerate it by utilizing a highly parallelized computation performed by GPGPUs. Through the experiments with designs from industry, our implementation on GPGPU runs 30 times faster than a software implementation.

Keywords

VLSI; graphics processing units; integrated circuit design; parallel processing; GPGPU; VLSI design; automatic assertion extraction; design correctness; design intention; gate-level simulation; graphics processing units; logical relation; parallelized computation; very large scale integration; Central Processing Unit; Educational institutions; Graphics processing units; Logic gates; Silicon; Simulation; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design (ICCD), 2012 IEEE 30th International Conference on

Conference_Location

Montreal, QC

ISSN

1063-6404

Print_ISBN

978-1-4673-3051-0

Type

conf

DOI

10.1109/ICCD.2012.6378704

Filename

6378704