Title :
Efficient microarchitecture policies for accurately adapting to power constraints
Author :
Cebrián, Juan M. ; Aragón, Juan L. ; García, José M. ; Petoumenos, Pavlos ; Kaxiras, Stefanos
Author_Institution :
Dept. of Comput. Eng., Univ. of Murcia, Murcia, Spain
Abstract :
In the past years dynamic voltage and frequency scaling (DVFS) has been an effective technique that allowed microprocessors to match a predefined power budget. However, as process technology shrinks, DVFS becomes less effective (because of the increasing leakage power) and it is getting closer to a point where DVFS won´t be useful at all (when static power exceeds dynamic power). In this paper we propose the use of microarchitectural techniques to accurately match a power constraint while maximizing the energy efficiency of the processor. We predict the processor power consumption at a basic block level, using the consumed power translated into tokens to select between different power-saving micro-architectural techniques. These techniques are orthogonal to DVFS so they can be simultaneously applied. We propose a two-level approach where DVFS acts as a coarse-grained technique to lower the average power while microarchitectural techniques remove all the power spikes efficiently. Experimental results show that the use of power-saving microarchitectural techniques in conjunction with DVFS is up to six times more precise, in terms of total energy consumed (area) over the power budget, than using DVFS alone for matching a predefined power budget. Furthermore, in a near future DVFS will become DFS because lowering the supply voltage will be too expensive in terms of leakage power. At that point, the use of power-saving microarchitectural techniques will become even more energy efficient.
Keywords :
low-power electronics; microprocessor chips; power aware computing; coarse-grained technique; dynamic voltage scaling; energy efficiency; frequency scaling; leakage power; microprocessors; power constraints; power-saving microarchitectural techniques; processor power consumption; two-level approach; Batteries; Dynamic voltage scaling; Energy consumption; Energy efficiency; Energy management; Frequency; Microarchitecture; Microprocessors; Process design; Thermal management;
Conference_Titel :
Parallel & Distributed Processing, 2009. IPDPS 2009. IEEE International Symposium on
Conference_Location :
Rome
Print_ISBN :
978-1-4244-3751-1
Electronic_ISBN :
1530-2075
DOI :
10.1109/IPDPS.2009.5161022