Adaptive Equalization Architecture Using Distributed Arithmetic for Partial Response Channels

Author

Chivapreecha, Sorawat ; Jaruvarakul, Aungkana ; Jaruvarakul, Nivat ; Dejhan, Kobchai

Author_Institution

Fac. of Eng., King Mongkut´´s Inst. of Technol., Bangkok

fYear

0

fDate

0-0 0

Firstpage

1

Lastpage

5

Abstract

This paper proposes a design and implementation of transversal adaptive digital filter using LMS (least mean squares) adaptive algorithm. The filter structure is based on distributed arithmetic (DA), which is able to calculate the inner product by shifting, and accumulating of partial products and storing in look-up table, also the desired adaptive digital filter will be multiplierless filter. In addition, the hardware implementation uses VHDL (very high-speed integrated circuit hardware description language) and synthesis using FLEX10K Altera FPGA (field programmable gate array) as target technology and uses Leonardo spectrum and MAX+plusII program for overall development. The results of this design are shown that the speed performance and used area of FPGA. The experimental results are presented to demonstrate the feasibility of the desired adaptive digital filter

Keywords

adaptive equalisers; adaptive filters; digital filters; distributed arithmetic; field programmable gate arrays; hardware description languages; least mean squares methods; partial response channels; table lookup; FLEX10K Altera FPGA; LMS adaptive algorithm; Leonardo spectrum; MAX+plusII program; VHDL; adaptive equalization architecture; distributed arithmetic; field programmable gate array; hardware description language; least mean squares; look-up table; multiplierless filter; partial response channel; transversal adaptive digital filter; very high-speed integrated circuit; Adaptive algorithm; Adaptive equalizers; Adaptive filters; Algorithm design and analysis; Arithmetic; Digital filters; Field programmable gate arrays; Least squares approximation; Partial response channels; Transversal filters; Adaptive Digital Filter; Distributed Arithmetic; FPGA; LMS Algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 2006. ISCE '06. 2006 IEEE Tenth International Symposium on

Conference_Location

St. Petersburg

Print_ISBN

1-4244-0216-6

Type

conf

DOI

10.1109/ISCE.2006.1689503

Filename

1689503