Title :
Energy Efficient Adiabatic Logic for Low Power VLSI Applications
Author :
Maurya, Atul Kumar ; Kumar, Gagnesh
Author_Institution :
Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Hamirpur, India
Abstract :
This paper proposes a Adder circuit based on energy efficient two-phase clocked adiabatic logic. a simulative investigation on the proposed 1-bit full adder has been implemented with the proposed technique and thence compared with standard CMOS, Positive Feedback Adiabatic Logic (PFAL) and Two-Phase Adiabatic Static Clocked Logic (2PASCL) respectively. Comparison has shown a significant power saving to the extent of 70% in case of proposed technique as compared to CMOS logic in 10 to 200MHz transition frequency range.
Keywords :
CMOS logic circuits; VLSI; adders; 2PASCL; CMOS technology; PFAL; adder circuit; energy efficient two-phase clocked adiabatic logic; frequency 10 MHz to 200 MHz; low power VLSI applications; positive feedback adiabatic logic; two-phase adiabatic static clocked logic; word length 1 bit; Adders; CMOS integrated circuits; Capacitance; Clocks; Inverters; Power dissipation; Very large scale integration; SPICE; adiabatic logic; energy recovery; power supply;
Conference_Titel :
Communication Systems and Network Technologies (CSNT), 2011 International Conference on
Conference_Location :
Katra, Jammu
Print_ISBN :
978-1-4577-0543-4
Electronic_ISBN :
978-0-7695-4437-3
DOI :
10.1109/CSNT.2011.100
