DocumentCode
2484679
Title
The world´s fastest CPU and SMP node: Some performance results from the NEC SX-9
Author
Zeiser, Thomas ; Hager, Georg ; Wellein, Gerhard
Author_Institution
Erlangen Regional Comput. Center, Univ. of Erlangen-Nuremberg, Erlangen, Germany
fYear
2009
fDate
23-29 May 2009
Firstpage
1
Lastpage
8
Abstract
Classic vector systems have all but vanished from recent TOP500 lists. Looking at the newly introduced NEC SX-9 series, we benchmark its memory subsystem using the low level vector triad and employ an advanced lattice Boltzmann flow solver kernel to demonstrate that classic vectors still combine excellent performance with a well-established optimization approach. Results for commodity x86-based systems are provided for reference.
Keywords
memory architecture; parallel machines; CPU; NEC SX-9; SMP node; lattice Boltzmann flow solver kernel; memory subsystem; optimization; vector architecture; x86-based system; Arithmetic; Bandwidth; CMOS technology; Computer buffers; Kernel; Lattice Boltzmann methods; National electric code; Registers; SDRAM; Supercomputers;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel & Distributed Processing, 2009. IPDPS 2009. IEEE International Symposium on
Conference_Location
Rome
ISSN
1530-2075
Print_ISBN
978-1-4244-3751-1
Electronic_ISBN
1530-2075
Type
conf
DOI
10.1109/IPDPS.2009.5161089
Filename
5161089
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