A Register Transfer Level Approach for Intermittent Semi-Concurrent Error Detection

With the increasing chip density and the continuous improvement of reliability requirements, the concurrent error detection techniques in register transfer level have become an increasing concern. Because of the actual low probability of failure occurring, a number of semi-concurrent error detection techniques are feasible. The circuits can be checked in every N iterations. So the recomputations will have N-1 free iterations. This paper can take full advantage of the free iterations to achieve the concurrent processing of the original computation, thus enhancing performance. The proposed strategy is actually independent from a specific scheduling-and-allocation algorithm; however, for recomputations the conventional duplication with comparison leads to high circuit complexity increase. So we modify the force-directed algorithm to ease the hardware overhead as well as to ensure that the data path is fault-secure in an iteration.