Parallel CLA algorithm for fast addition

Author

Manzoul, Mahmoud A.

Author_Institution

Sch. of Eng., American Univ. of Sharjah, United Arab Emirates

fYear

2000

fDate

2000

Firstpage

55

Lastpage

58

Abstract

The carry look-ahead (CLA) is a popular addition algorithm in the Arithmetic and Logic Unit (ALU) of computers. The algorithm is based on the computation of the carries using one CLA circuit. In the paper, a parallel version of the CLA circuit is presented. Two, three or four parallel CLA circuits may be employed in the computation of the carries. The computations of the carries are equally divided among the parallel CLA circuits. Despite the inclusion of non-binary logic the presented parallel algorithm is completely realizable by binary gates. The different versions of the parallel CLA algorithm and the conventional CLA algorithm are compared in terms of gate delays

Keywords

carry logic; delays; digital arithmetic; logic gates; parallel algorithms; Arithmetic and Logic Unit; CLA circuit; binary gates; carry look-ahead algorithm; fast addition; gate delays; nonbinary logic; parallel CLA algorithm; Added delay; Adders; Circuits; Concurrent computing; Digital arithmetic; Equations; Logic; Parallel algorithms; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Computing in Electrical Engineering, 2000. PARELEC 2000. Proceedings. International Conference on

Conference_Location

Trois-Rivieres, Que.

Print_ISBN

0-7695-0759-X

Type

conf

DOI

10.1109/PCEE.2000.873601

Filename

873601