Hardware optimization of Generalized Pairwise Complementary sequences generation

Generalized Pairwise Complementary (GPC) sequences are increasingly being used in many applications due to their properties, which allow uncorrelated sequences generation from a base pair. The generation of these sequences is conducted by iterative algorithms developed to be implemented in hardware platforms. However, in order to reduce even further the amount of resources required for the implementation, these algorithms can be improved with digital synthesis as the final goal. This work proposes an improved GPC sequences generator developed for FPGA platforms, which notoriously reduces resources requirements by applying some concepts developed for Golay sequences generation. FPGA implementation is performed with generic parameters to evaluate and compare it with the straightforward approach.