Input switch configuration for sample and hold circuits in low-voltage operation

Author

Lagziri, Manal ; Dualibe, F.C. ; Moreno, Eugenio G.

Author_Institution

Electron. Eng. Group, Univ. of Balearic Islands, Palma de Mallorca, Spain

fYear

2014

fDate

24-25 July 2014

Firstpage

107

Lastpage

112

Abstract

This work presents an implementation of Dessouky´s bootstrapped switch optimized for 65-nm CMOS technology to attain a high linearity in front-end sample-and-hold (S/H) circuits [6]. The simulations of this design show that the spurious-free dynamic range (SFDR) achieves 100 dB for a single sinusoidal input signal of 36.36 MHz at f_s=80 MHz.

Keywords

CMOS integrated circuits; bootstrap circuits; low-power electronics; sample and hold circuits; semiconductor switches; CMOS technology; Dessouky bootstrapped switch; front-end sample-and-hold circuits; input switch configuration; low-voltage operation; size 65 nm; spurious-free dynamic range; CMOS integrated circuits; CMOS technology; Educational institutions; Logic gates; Switches; Switching circuits; Transistors; Analog-to-digital converters; bootstrapped switch; low-voltage operation; sample-and-hold circuit;

fLanguage

English

Publisher

ieee

Conference_Titel

Micro-Nanoelectronics, Technology and Applications (EAMTA), 2014 Argentine Conference on

Conference_Location

Mendoza

Print_ISBN

978-987-1907-86-1

Type

conf

DOI

10.1109/EAMTA.2014.6906087

Filename

6906087

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=248531