A simulated annealing based technology mapping method for sequential circuits

Author

Li, Peng ; Lan, Julong ; Li, Dan ; Liu, Qiang

Author_Institution

Nat. Digital Switching Syst. Eng. & Technol. Res. Center, Zhengzhou, China

fYear

2009

fDate

14-17 Oct. 2009

Firstpage

303

Lastpage

307

Abstract

Due to the rapid growth of traffic in Internet, backbone links of 40 gigabits per second are commonly deployed. To handle high traffic rates, the backbone routers must be able to forward millions of packets per second on each of their ports. Pipelined design can effectively support high speed packets processing. Technology mapping method for sequential circuits in FPGA is playing vital role to pipelined design. This paper presents a simulated annealing based technology mapping method for sequential circuits. The proposed method not only guarantees minimal clock period for pipeline level, but also saves FPGA resources.

Keywords

field programmable gate arrays; pipeline processing; sequential circuits; simulated annealing; telecommunication links; telecommunication network routing; telecommunication traffic; FPGA; Internet traffic; backbone links; backbone routers; high-speed packet processing; minimal clock period; pipelined design; sequential circuits; simulated annealing; technology mapping method; Circuit simulation; Clocks; Field programmable gate arrays; Programmable logic arrays; Programmable logic devices; Sequential circuits; Simulated annealing; Space technology; Table lookup; Traffic control; pipeline; retiming; sequential technology mapping; simulated annealing;

fLanguage

English

Publisher

ieee

Conference_Titel

Future Information Networks, 2009. ICFIN 2009. First International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-5158-6

Electronic_ISBN

978-1-4244-5159-3

Type

conf

DOI

10.1109/ICFIN.2009.5339593

Filename

5339593