Verifying finite state real-time discrete event processes

Decision procedures are presented for checking a small but useful class of properties for any finite-state system consisting of real-time discrete-event processes. A timed transition model (TTM) is used for representing real-time discrete-event processes, and real-time temporal logic (RTTL) is the assertion language in which the property to be verified is stated. The relationship of TTMs to other formalisms is summarized along with a complete definition of TTMs and an overview of RTTL. The construction of reachability graphs is discussed, two different procedures are presented for constructing reachability graphs, and the corresponding decision procedures are given