DocumentCode :
2485794
Title :
Two-bounce free-space arbitrary interconnection architecture
Author :
Christensen, Marc P. ; Haney, Michael W.
Author_Institution :
Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA
fYear :
1997
fDate :
22-24 June 1997
Firstpage :
61
Lastpage :
67
Abstract :
The two bounce free-space arbitrary interconnection architecture is introduced. It is requires 3 stages of local electronic routing and 2 passes, or bounces, through a common retro-reflective optical system. The concept combines the global optical interconnection with the minimum nonblocking multistage interconnection network, the Benes network, to achieve arbitrary interconnections across a multichip backplane. The arbitrary interconnection requires only one additional pass through the optical system. The architecture is experimentally validated with a optical module and a fiber coupled LED and detector array to simulate the smart pixel I/O placement in the backplane of the module. The architecture is further evaluated using VCSEL arrays and a CCD camera for resolution and registration measurements.
Keywords :
multistage interconnection networks; optical interconnections; surface emitting lasers; Benes network; CCD camera; VCSEL arrays; arbitrary interconnection; free-space; global optical interconnection; interconnection architecture; minimum nonblocking; multichip backplane; multistage interconnection network; two bounce; Backplanes; Light emitting diodes; Multiprocessor interconnection networks; Optical arrays; Optical coupling; Optical interconnections; Routing; Sensor arrays; Smart pixels; Vertical cavity surface emitting lasers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Massively Parallel Processing Using Optical Interconnections, 1997., Proceedings of the Fourth International Conference on
Print_ISBN :
0-8186-7975-1
Type :
conf
DOI :
10.1109/MPPOI.1997.609099
Filename :
609099
Link To Document :
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