Improvement of simultaneous switching noise simulation considering on-chip capacitance

Simultaneous switching noise (SSN) causes signal degradation to the high-speed interfaces among CMOS VLSIs. To achieve SSN simulation with a high accuracy, accurate models for chips, packages and printed circuit boards (PCBs) are required. However, such accurate simulation models are not currently available, since chip vendors do not release the value of on-chip capacitance and the detailed package model with mutual inductances. This paper presents our approach for establishing an accurate model without detailed information on the chip and package. The three key points of our approach are the measurement of on-chip capacitance using a vector network analyzer (VNA), the measurement of quad flat package (QFP) dimensions using X-ray photographs, and the application of 3-D electromagnetic field solver to extract a detailed equivalent circuit model for the package from a geometrical structure. The simulated SSN time-domain waveforms showed an extremely good agreement with the measured results.