A high speed architecture for MAP decoder

In this paper, a new high speed MAP decoder architecture is presented. The speed in the MAP decoder is limited by the recursive iteration loop which updates the state metrics. Lookahead transformation technique alleviates the limitation of the recursive loop by expanding it in time. The focus in this paper is on the design of MAP decoder architecture based on lookahead transformation. One level of lookahead is applied that can process two updating trellis iterations at the same time. Resulting in improving the throughput and reducing the state metric memory. This technique is limited by the increased complexity of the add-compare-select-add (ACSA) unit. Design of less complex ACSA is presented, also the MAP decoder based on the look-ahead is prototyped on Xilinx FPGA.