A scalable system architecture for high-throughput turbo-decoders

The need for higher data rates is ever rising as wireless communication standards move from the third to the fourth generation. turbo-codes are the prevalent channel codes for wireless systems due to their excellent forward error correction capability. So far research has mainly focused on components of high throughput turbo-decoders. To the best of our knowledge, no complete turbo-decoder system has been targeted. In this paper we explore the turbo-decoder design space anew, both under system design and deep-submicron implementation aspects. Our approach incorporates all levels of design, from I/O behavior down to floorplanning and deep-submicron effects in synthesis and interconnect. Its scalability allows to derive optimized architectures tailored to the given throughput and target technology. We present a design example for a 60 Mbit/s 3GPP compliant turbo-decoder synthesized on a 0.18 μm standard cell library.