Instruction and hardware acceleration for MP-MLQ in G.723.1

Author

Olausson, Mikael ; Liu, Dake

Author_Institution

Dept. of Electr. Eng., Linkoping Univ., Sweden

fYear

2002

fDate

16-18 Oct. 2002

Firstpage

235

Lastpage

239

Abstract

This paper describes a significant improvement in complexity for the higher bit rate, 6.3 kbit/s, speech coding algorithm G.723.1. The solution is to reduce the number of multiplications of the most computing extensive part of the algorithm. This part stands for around 50% of the total complexity. This is done by identifying and excluding multiplication with zeros. G.723.1 is one of the proposed speech coders in the H.323 standard. The work has been done by thoroughly examining the fixed point source code from ITU, International Telecommunication Unions. A hardware structure for an application specific instruction set processor (ASIP) is proposed to increase the performance.

Keywords

application specific integrated circuits; instruction sets; maximum likelihood estimation; quantisation (signal); speech coding; 6.3 kbit/s; G.723.1; H.323 standard; ITU; MP-MLQ; application specific instruction set processor; bit rate; complexity; fixed point source code; hardware acceleration; multi-pulse maximum likelihood quantization; speech coding algorithm; Acceleration; Application specific processors; Bit rate; Code standards; Codecs; Couplings; Delay; Hardware; Speech coding; Telecommunications;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2002. (SIPS '02). IEEE Workshop on

ISSN

1520-6130

Print_ISBN

0-7803-7587-4

Type

conf

DOI

10.1109/SIPS.2002.1049715

Filename

1049715