DocumentCode
2486956
Title
Fast acquisition PLL synthesizer using parallel N-stage cycle swallower (NSCS)
Author
Saba, Takahiko ; Park, Duk-Kyu ; Mori, Shinsaku
Author_Institution
Dept. of Electr. Eng., Keio Univ., Yokohama, Japan
fYear
1994
fDate
4-6 Jul 1994
Firstpage
352
Abstract
A phase-locked loop (PLL) frequency synthesizer with an N-stage cycle swallower (NSCS) is one of the fastest frequency switching synthesizers, but the use of the NSCS results in high power consumption and phase noise in the UHF band. This paper elucidates these problems and proposes a fast-acquisition PLL synthesizer using a novel type of NSCS with low power consumption and low phase noise. Experimental results confirm that the use of a parallel NSCS and a prescalar results in greatly reduced power consumption and phase noise
Keywords
frequency hop communication; frequency synthesizers; phase locked loops; phase noise; prescalers; radio receivers; voltage-controlled oscillators; UHF band; fast acquisition PLL synthesizer; frequency synthesizer; high power consumption; low power consumption; parallel N-stage cycle swallower; phase noise; phase-locked loop; prescalar; switching synthesizers; Bandwidth; Communication switching; Energy consumption; Frequency synthesizers; Output feedback; Phase detection; Phase frequency detector; Phase locked loops; Phase noise; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Spread Spectrum Techniques and Applications, 1994. IEEE ISSSTA '94., IEEE Third International Symposium on
Conference_Location
Oulu
Print_ISBN
0-7803-1750-5
Type
conf
DOI
10.1109/ISSSTA.1994.379565
Filename
379565
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