• DocumentCode
    2487071
  • Title

    Achieving network on chip fault tolerance by adaptive remapping

  • Author

    Ababei, Cristinel ; Katti, Rajendra

  • Author_Institution
    Electr. & Comput. Eng. Dept., North Dakota State Univ., Fargo, ND, USA
  • fYear
    2009
  • fDate
    23-29 May 2009
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper investigates achieving fault tolerance by adaptive remapping in the context of networks on chip. The problem of dynamic application remapping is formulated and an efficient algorithm is proposed to address single and multiple PE failures. The new algorithm can be used to dynamically react and recover from PE failures in order to maintain system functionality. The quality of results is similar to that achieved using simulated annealing but in significantly shorter runtimes.
  • Keywords
    failure analysis; fault tolerance; integrated circuit design; network-on-chip; simulated annealing; NoC fault tolerance; adaptive remapping; dynamic application remapping; multiple PE failure recovery; network on chip design; simulated annealing; system functionality; Application software; Computer networks; Energy consumption; Fault tolerance; Neodymium; Network-on-a-chip; Routing; Simulated annealing; Thermal stresses; Tiles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel & Distributed Processing, 2009. IPDPS 2009. IEEE International Symposium on
  • Conference_Location
    Rome
  • ISSN
    1530-2075
  • Print_ISBN
    978-1-4244-3751-1
  • Electronic_ISBN
    1530-2075
  • Type

    conf

  • DOI
    10.1109/IPDPS.2009.5161202
  • Filename
    5161202