Bridging the testing speed gap: design for delay testability

Author

Speek, H. ; Kerkhoff, H.G. ; Sachdev, M. ; Shashaani, M.

Author_Institution

MESA Res. Inst., Twente Univ., Enschede, Netherlands

fYear

2000

fDate

2000

Firstpage

3

Lastpage

8

Abstract

The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a design for delay testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. Also extensions for possible full BIST of delay faults are addressed

Keywords

automatic test equipment; automatic test pattern generation; built-in self test; delays; design for testability; flip-flops; high-speed integrated circuits; integrated circuit testing; integrated logic circuits; logic testing; ATPG; clock control; controlled delay scan flip-flop; delay faults; design for delay testability; economic testing; embedded sequential blocks; full BIST; high-speed digital IC; low-speed ATE; programmable delay line; programmable duty-cycle control; testing speed gap; Built-in self-test; Circuit faults; Circuit testing; Clocks; Costs; Delay effects; Electrical fault detection; Flip-flops; Frequency; Logic testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Workshop, 2000. Proceedings. IEEE European

Conference_Location

Cascais

ISSN

1530-1877

Print_ISBN

0-7695-0701-8

Type

conf

DOI

10.1109/ETW.2000.873771

Filename

873771