DocumentCode
2487977
Title
LEAP: An accurate defect-free IDDQ estimator
Author
Ferré, Antoni ; Figueras, Joan
Author_Institution
Dept. d´´Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
fYear
2000
fDate
2000
Firstpage
33
Lastpage
38
Abstract
The quiescent current (IDDQ) consumed by a CMOS IC is a good indicator of the presence of a large class of defects. However, the effectiveness of IDDQ testing requires appropriate discriminability of defective and defect-free currents, and hence it becomes necessary to estimate the currents involved in order to design the IDDQ test. In this work, we present a method to estimate accurately the non-defective IDDQ consumption based on a hierarchical approach at electrical (cell) and logic (circuit) levels. This accurate estimator is used in conjunction with an ATPG to obtain vectors having low/high defect-free IDDQ currents
Keywords
CMOS logic circuits; SPICE; automatic test pattern generation; integrated circuit testing; logic simulation; logic testing; ATPG; CMOS IC; CMOS logic; LEAP tool; Monte-Carlo simulation; SPICE; accurate defect-free IDDQ estimator; cell level; defect-free currents; defective currents; greedy algorithm; hierarchical approach; logic level; logic simulator; quiescent current testing; search algorithm; vectors; CMOS logic circuits; Foundries; Histograms; Libraries; Logic circuits; MOS devices; MOSFETs; Rails; Semiconductor device modeling; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Workshop, 2000. Proceedings. IEEE European
Conference_Location
Cascais
ISSN
1530-1877
Print_ISBN
0-7695-0701-8
Type
conf
DOI
10.1109/ETW.2000.873776
Filename
873776
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