Title :
Towards an ADC BIST scheme using the histogram test technique
Author :
Azaïs, F. ; Bernard, S. ; Betrand, Y. ; Renovell, M.
Author_Institution :
LIRMM, Montpellier Univ., France
Abstract :
This paper discusses the viability of a BIST implementation for the sinusoidal histogram technique classically used for ADC testing. An original approach based on (i) approximations to estimate the ADC parameters, (ii) decomposition of the global test in a code-after-code test procedure and (iii) piecewise approximation to compute the ideal histogram is developed. These three features allow a significant reduction of the required operative resources as well as the required memory resources dedicated to the storage of both experimental and reference data
Keywords :
analogue-digital conversion; automatic testing; built-in self test; integrated circuit testing; piecewise polynomial techniques; ADC testing; BIST implementation; code density method; code-after-code test procedure; global test decomposition; ideal histogram; minimum hardware resources; piecewise approximation; sinusoidal histogram technique; Analog-digital conversion; Automatic testing; Built-in self-test; Circuit testing; Costs; Histograms; Linearity; Parameter estimation; Production; Test equipment;
Conference_Titel :
Test Workshop, 2000. Proceedings. IEEE European
Conference_Location :
Cascais
Print_ISBN :
0-7695-0701-8
DOI :
10.1109/ETW.2000.873779
