A multi-port RAM generator with novel memory cell for CMOS Sea-of-Gates

Author

Nii, Koji ; Maeno, Hideshi ; Osawa, Tokuya ; Iwade, Syuuhei

Author_Institution

Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan

fYear

1994

fDate

1-4 May 1994

Firstpage

667

Lastpage

670

Abstract

A multi-port RAM generator for 0.5 μm CMOS Sea-of-Gates (SOG) has been developed. 2-port or 3-port RAMs with flexible bit-word configurations are available. In order to operate either at a low supply voltage or at high speed, a novel memory cell circuit is proposed. In addition, a fourfold real bit line technique is adopted to improve access time. The experimental results of the test chips show that each generated RAM operates at over 1.4 V and that the address access time of the 3-port RAM (16 b×256 w) is 4.8 ns at 3.3 V

Keywords

CMOS memory circuits; application specific integrated circuits; cellular arrays; integrated circuit layout; random-access storage; 0.5 micron; 1.4 to 3.3 V; 4.8 ns; 4096 bit; CMOS sea-of-gates; SOG array; access time; flexible bit-word configurations; fourfold real bit line technique; high speed; low supply voltage; memory cell; multi-port RAM generator; Application specific integrated circuits; Buffer storage; Cache memory; Circuit testing; Large scale integration; Low voltage; MOSFETs; Random access memory; Read only memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379635

Filename

379635