Compressed bit fail maps for memory fail pattern classification

Author

Vollrath, Jörg ; Lederer, Ulf ; Hladschik, Thomas

fYear

2000

fDate

2000

Firstpage

125

Lastpage

130

Abstract

This paper presents a new approach to configure compressed bit fail maps to allow fail pattern recognition. Construction of the special compression scheme is shown. This takes typical memory array fail patterns into account. Examples for different failure types are given. This scheme allows minimizing the necessary cache memory size for fail classification. A 64 Mbit fail map can be compressed to 2 k allowing classification of 13 fail types. Since cache RAM requirements are small, this scheme can be implemented in a manufacturing environment for all processed hardware. Compressed bit fail maps can be used to generate wafer and lot maps for diagnosis

Keywords

DRAM chips; SRAM chips; automatic testing; cache storage; data compression; failure analysis; pattern classification; cache RAM requirements; cache memory size; compressed bit fail maps; compression scheme; lot maps; memory array fail patterns; memory fail pattern classification; production environment; signature analysis; wafer maps; Hardware; Image coding; Image storage; Manufacturing processes; Mass production; Pattern classification; Pattern recognition; Random access memory; Semiconductor device manufacture; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Workshop, 2000. Proceedings. IEEE European

Conference_Location

Cascais

ISSN

1530-1877

Print_ISBN

0-7695-0701-8

Type

conf

DOI

10.1109/ETW.2000.873789

Filename

873789