DocumentCode
2488277
Title
A method for trading off test time, area and fault coverage in datapath BIST synthesis
Author
Berthelot, D. ; Flottes, M.L. ; Rouzeyre, B.
Author_Institution
Lab. d´´Inf., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
fYear
2000
fDate
2000
Firstpage
133
Lastpage
139
Abstract
This paper presents a method for deriving a BIST specification from the initial specification of datapaths. This method minimizes BIST area overhead under test time constraint while guaranteeing a user chosen fault coverage. The designer can thus explore a wide range of solutions and keep the one that best fits with design constraints. Results show great improvements over lower level techniques
Keywords
automatic test pattern generation; built-in self test; data flow graphs; fault diagnosis; high level synthesis; BIST insertion; BIST specification; branch and bound; datapath BIST synthesis; design constraints; fault coverage; high level synthesis; initial specification of datapaths; scheduled data flow graph; test area; test time; Arithmetic; Built-in self-test; Circuit testing; Compaction; Degradation; High level synthesis; Logic testing; Robots; Test pattern generators; Time factors;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Workshop, 2000. Proceedings. IEEE European
Conference_Location
Cascais
ISSN
1530-1877
Print_ISBN
0-7695-0701-8
Type
conf
DOI
10.1109/ETW.2000.873790
Filename
873790
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