Title :
A method for trading off test time, area and fault coverage in datapath BIST synthesis
Author :
Berthelot, D. ; Flottes, M.L. ; Rouzeyre, B.
Author_Institution :
Lab. d´´Inf., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Abstract :
This paper presents a method for deriving a BIST specification from the initial specification of datapaths. This method minimizes BIST area overhead under test time constraint while guaranteeing a user chosen fault coverage. The designer can thus explore a wide range of solutions and keep the one that best fits with design constraints. Results show great improvements over lower level techniques
Keywords :
automatic test pattern generation; built-in self test; data flow graphs; fault diagnosis; high level synthesis; BIST insertion; BIST specification; branch and bound; datapath BIST synthesis; design constraints; fault coverage; high level synthesis; initial specification of datapaths; scheduled data flow graph; test area; test time; Arithmetic; Built-in self-test; Circuit testing; Compaction; Degradation; High level synthesis; Logic testing; Robots; Test pattern generators; Time factors;
Conference_Titel :
Test Workshop, 2000. Proceedings. IEEE European
Conference_Location :
Cascais
Print_ISBN :
0-7695-0701-8
DOI :
10.1109/ETW.2000.873790
