Title :
A new efficient routing method for channel-less sea-of-gates arrays
Author :
Terai, Masayuki ; Takahashi, Kazuhiro ; Shirota, Hiroshi ; Sato, Koji
Author_Institution :
Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A fast router (termed HGALOP router) for CMOS triple-metal-layer sea-of-gates (SOG) arrays is reported. The HGALOP router employs an algorithm which efficiently utilizes the regularity in layout structures of channel-less SOG chips, and, on average, is 10 times faster than the commercially available router which is commonly used by ASIC makers. The layout structures that the router deals with and the routing algorithm is outlined. The effectiveness of our method is demonstrated by our experimental results on industrial SOG chips and a well-known benchmark circuit
Keywords :
CMOS logic circuits; application specific integrated circuits; cellular arrays; circuit layout CAD; integrated circuit layout; logic CAD; logic arrays; network routing; ASIC; CMOS triple-metal-layer SOG arrays; HGALOP router; channelless SOG arrays; layout structures; routing method; sea-of-gates arrays; Application specific integrated circuits; Flip-flops; Integrated circuit interconnections; Joining processes; Laboratories; Large scale integration; Logic functions; Macrocell networks; Routing; Wires;
Conference_Titel :
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1886-2
DOI :
10.1109/CICC.1994.379639
