Power integrity analysis of TSV based 3-D integrated circuits

The power supply grids of integrated circuits (ICs) are interconnected through silicon vias (TSVs) to form a 3-D chip integration in vertical direction. The required currents for each functional device to operate in the ICs are supplied through power and ground TSV pairs and power distribution meshes. Accurate estimation of power/ground noises (static and dynamic drops) in a 3-D power distribution network is crucial for a robust power supply design in order to operate the devices functionally. With fast switching characteristics of the devices, the worst case power supply noise may not be analysed accurately. In this paper, we present a systematic approach to analyse the static and dynamic drop, as a function of switching time, in power supply grids of 3-D ICs. Furthermore the approach is extended to investigate noise sensitivity of TSVs and power supply grids with decoupling capacitors.