An efficient self-timed queue architecture for ATM switch LSI´s

Author

Kondoh, Harufusa ; Yamanaka, Hideaki ; Ishiwaki, Masahiko ; Matsuda, Yoshio ; Nakaya, Masao

Author_Institution

Syst. LSI Lab., Mitsubishi Electr. Corp., Itami, Japan

fYear

1994

fDate

1-4 May 1994

Firstpage

637

Lastpage

640

Abstract

A new approach to implement queues for controlling ATM switch LSI is presented. We combined a self-timed FIFO with a search circuit that finds the earliest entry for each output port. Using this architecture, queues provided for each output port can be effectively realized by a single FIFO. The delay priority and multicasting are supported without doubling the number of the queues. This new FIFO can also be utilized as an ATM switch by itself. Evaluation chip was fabricated using 0.5-μm CMOS process technology. Interstage transfer speed over 500 MHz and cycle time over 125 MHz were obtained

Keywords

B-ISDN; CMOS digital integrated circuits; asynchronous transfer mode; electronic switching systems; field effect transistor switches; large scale integration; 0.5 micron; 125 MHz; 500 MHz; ATM switch LSI; CMOS process technology; delay priority; multicasting; search circuit; self-timed FIFO; self-timed queue architecture; Asynchronous transfer mode; B-ISDN; CMOS technology; Circuits; Communication switching; Communication system control; Delay; Laboratories; Large scale integration; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379642

Filename

379642